Generation of symbolic cell layout by rule-based approach

Abstract

This thesis focuses on the problem of CMOS cell layout and describes the system to generate cell layouts automatically. The input of desired cell layout is specified in terms of circuit components and their interconnections using netlist form. From this input, the system generates symbolic cell layout description. The cell layout is based on the single metal, single polysilicon CMOS technology. Although the implementation of this system has focused on various logic types of CMOS such as the static and the dynamic logic, the proposed techniques can be used for other technologies. The layout style is similar to the gate matrix layout. This style is orderly and regular, therefore complexity of the layout generation and verification can be reduced to some degree and it is suitable for the automation of the cell layout. To cope with the complexity of the cell layout, this system is divided into several modules. These modules are specialized for their own tasks, but related closely with each other. This system is implemented in OPS5, a general purpose rule-based language, and LISP.