DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, Kyu-Ho | - |
dc.contributor.advisor | 박규호 | - |
dc.contributor.author | Kim, Jae-Hoon | - |
dc.contributor.author | 김재훈 | - |
dc.date.accessioned | 2011-12-14T02:12:09Z | - |
dc.date.available | 2011-12-14T02:12:09Z | - |
dc.date.issued | 1987 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65729&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/38994 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1987.2, [ [iii], 87 p. ] | - |
dc.description.abstract | There have been proposed many models for parallel execution of logic programs. Among them, the most natural model for parallel execution of logic programs is the AND/OR process model. An experimental simulator is designed which is based on Conery``s AND/OR process model. But, recently, it is proved that this backtracking scheme is not correct by several researchers. In this thesis, Lin``s scheme for intelligent backtracking is implemented on the experimental simulator. The simulator is written in CPROLOG 1.5 language. It divides a logic program by set of of processes and performs transitions of processes by reading messages. Behaviors of the simulator is not parallel because of current PROLOG. The simulator shows the degree of parallelism where AND and OR parallelisms are exploited to solve logic programs. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | (An) experimental simulator for AND/OR process model | - |
dc.title.alternative | AND/OR 프로세스 모델의 실험적 모의수행 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 65729/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000851078 | - |
dc.contributor.localauthor | Park, Kyu-Ho | - |
dc.contributor.localauthor | 박규호 | - |
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