ED MOS 논리 LSI의 지연시간 모델링과 다지연 논리 시뮬레이터Delay time modeling for ED MOS logic LSI and multiple delay logic simulator

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dc.contributor.advisor박송배-
dc.contributor.advisorPark, Song-Bai-
dc.contributor.author김경호-
dc.contributor.authorKim, Kyung-Ho-
dc.date.accessioned2011-12-14T02:11:58Z-
dc.date.available2011-12-14T02:11:58Z-
dc.date.issued1987-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65717&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/38982-
dc.description학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1987.2, [ iii, 65 p. ]-
dc.languagekor-
dc.publisher한국과학기술원-
dc.titleED MOS 논리 LSI의 지연시간 모델링과 다지연 논리 시뮬레이터-
dc.title.alternativeDelay time modeling for ED MOS logic LSI and multiple delay logic simulator-
dc.typeThesis(Master)-
dc.identifier.CNRN65717/325007-
dc.description.department한국과학기술원 : 전기 및 전자공학과, -
dc.identifier.uid000841024-
dc.contributor.localauthor박송배-
dc.contributor.localauthorPark, Song-Bai-
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EE-Theses_Master(석사논문)
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