Analysis and architecture design of binary arithmetic coder for JPEG2000

Abstract

The embedded-block coding with optimized truncation (EBCOT) employed in the JPEG2000 standard is the major bottleneck in realizing a high-throughput JPEG2000 encoding system, because it accounts for the majority of the processing time. The EBCOT consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC). As the up-to-date BPC architectures can produce symbols at a much higher rate than the conventional BAC architectures can handle, several pipelined BAC architectures have been suggested to reduce the performance gap either by encoding multiple symbols per cycle or by encoding a single symbol at a faster rate. In this thesis, two optimization schemes named as trace pipelining and renormalization look-ahead, that are effective in optimizing arithmetic coding and thus implementing JPEG2000 encoders are proposed. Two novel BAC architecture based on the proposed methods are also suggested to show the efficiency of the proposed methods. The first version is a single-symbol BAC that encodes a single input pair per clock cycle, and the second version is a dual-symbol BAC that encodes two of the input pairs simultaneously. The proposed single-symbol / dual-symbol BAC architectures can reduce the critical path delay significantly and can achieve a throughput of 400M symbols/sec and 500M symbols/sec respectively, which is much higher than conventional BAC architectures are capable of. The critical path delay of the proposed single-symbol / dual-symbol BAC synthesized with 0.18-$\mu$m CMOS technology is 2.42 ns and 3.68 ns respectively, which are almost half the delay taken in conventional BAC architectures.