Reference multiplied PLL and phase filtered harmonic locking for low noise frequency synthesizer저잡음 주파수 합성기를 위한 기준 주파수 증폭된 위상 고정 루프와 위상 필터된 조화 고정

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dc.contributor.advisorCho, Seong-Hwan-
dc.contributor.advisor조성환-
dc.contributor.authorLee, Woo-Jae-
dc.contributor.author이우재-
dc.date.accessioned2011-12-14T02:08:04Z-
dc.date.available2011-12-14T02:08:04Z-
dc.date.issued2009-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=308842&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/38722-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ viii, 66 p. ]-
dc.description.abstractThis thesis presents several architecture which improve the phase noise performance of frequency synthesizer. To decrease the phase noise of frequency synthesizer which is based on phase locked loop(PLL), reference frequency multiplying technique is used. Three architectures are described to implement the idea. First is to use multi-phase injection locked oscillator(ILO). By using multi-phase ILO, phase errors were compared 8 times within a reference frequency. To use both negative edge and positive edge of the reference signal, reference doubler and differential divider output is proposed. These architectures can reduce the phase noise from both charge pump and $\Delta - \Sigma$ modulator noise at the same time. The simulation results shows that proposed architecture has a good phase noise reduction performance. In addition, direct frequency synthesizer is proposed. This architecture can overcome the disadvantages of direct digital frequency synthesizer(DDFS) by using phase filter and injection locking oscillator. These architectures were implemented in $0.13 \mu m$ CMOS process.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectreference multiplied-
dc.subjectPLL-
dc.subjectphase filter-
dc.subjectharmonic locking-
dc.subjectfrequency synthesizer-
dc.subject기준 주파수 증폭-
dc.subject위상고정루프-
dc.subject위상 필터-
dc.subject조화 고정-
dc.subject주파수 합성기-
dc.subjectreference multiplied-
dc.subjectPLL-
dc.subjectphase filter-
dc.subjectharmonic locking-
dc.subjectfrequency synthesizer-
dc.subject기준 주파수 증폭-
dc.subject위상고정루프-
dc.subject위상 필터-
dc.subject조화 고정-
dc.subject주파수 합성기-
dc.titleReference multiplied PLL and phase filtered harmonic locking for low noise frequency synthesizer-
dc.title.alternative저잡음 주파수 합성기를 위한 기준 주파수 증폭된 위상 고정 루프와 위상 필터된 조화 고정-
dc.typeThesis(Master)-
dc.identifier.CNRN308842/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020073408-
dc.contributor.localauthorCho, Seong-Hwan-
dc.contributor.localauthor조성환-
Appears in Collection
EE-Theses_Master(석사논문)
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