Slicing-DVS

Abstract

The ever increasing leakage power and chip temperature are becoming important issues for high performance and low power SoC design. However, the traditional DVS method widely recognized as a means of reducing power consumption does not consider the dependence of leakage power on the chip temperature impacts. In this paper, we propose a temperature-aware DVS algorithm which inserts slacks of near optimal length into a task. Experiment shows that proposed algorithm achieves an energy reduction of 45% over traditional DVS method and energy reduction of 10% over the state-of-the-art algorithm.