Technology mapping for morphed regular architecture

Abstract

Cell based design broadly used for designing ASIC because of its high performance, low power consumption, high density. However, its design cost increases exponentially as feature size getting smaller and smaller. The two main factors for this increase are engineering cost & mask cost. The total number of transistors increases with technology scaling so design becomes complicated. In the mask case, mask carving cost increases because of RETs (OPC, PSM, etc.) from the 100nm technology. In addition, mask cycle time also increases so the time-on-market becomes too long. To solve these problems - increasing cost and time-on-market- we can consider array based designs like gate array, FPGA, etc. Array based design has very low NRE cost and short time-on-market. In addition, its structure is regular so that we need not to spend on calculating OPC, PSM, etc. However, these array based designs are very slow, or too area wasting, so these can’t substitute cell based design. Recently, structured ASIC has been developed to reduce gap between array based design and cell based design. However, several conventional approaches are not enough to alternate cell based design yet because of its area overhead. In this thesis, we propose new structured ASIC which is much smaller than conventional method and its logic synthesis flow. Our proposed cell is much faster than conventional via programmable cells because it is programmed by contact positioning not via. Moreover, we suggest technology mapping which adjusts cell packing characteristics so that total area can be reduced. We succeed to balance the circuit with gate statistics of the circuit and the results showed only 27% area increase for an average while conventional approaches shows 300% area increase for an average.