(A) 100 to 200 MHz area-efficient LC-VCO based clock generator in 130nm CMOS

Abstract

This paper presents an area-effcient clock generator based on LC-VCO for low power, high frequency resolution and low jitter. For wide range of the clock output frequency, 100~200MHz, the proposed architecture indirectly produces the clock output through the clock divider from a LC-VCO operating high frequency to reduce inductor size. As the clock divider is placed in the feedback loop, it can reduce the power consumption of the clock divider without additional clock divider comparing the conventional structure. The method to reduce die area due to the inductor occupying large silicon area is introduced. As placing the on-chip loop filter having a large area occupation underneath the inductor of LC-VCO, the clock generator can raise the area efficiency in the proposed architecture.