On-chip Low-Power Sub-picosecond Jitter-Measurement circuit for Low-Jitter clock generator

Abstract

To achieve low jitter in phase-locked loop (PLL), many techniques to fix loop characteristics over frequency range were introduced, but could not achieve lowest jitter over whole range because of design margins to be robust against process variations, non-linearity of PLL components, etc. Jitter-minimizing scheme with jitter-measurement can achieve minimum jitter with given conditions, but has not been popularly used because of limitation of jitter-measurement circuit. This thesis proposes an on-chip sub-picosecond jitter-measurement circuit with RC-delay lines. It can achieve sub-picosecond resolution (0.88ps ~ 8.8ps) consuming 1.7-mW, and its area is 0.027 mm2. Its non-ideal effects are analyzed, and some techniques are presented and implemented to solve those non-ideal effects.