Design of RISC microprocessor and graphics system using board level simulation

Abstract

A lot of efforts were offered in developing efficient design methods of VLSI and system, in order to reduce design time and chip revision cost. However it is difficult to reduce these any more with existing methods. This thesis introduces a board level simulation technique in design methodology of VLSI and system to reduce these with concurrent engineering. As an example of board level simulation, the GISC chip which is a RISC microprocessor and the GISC system which is a graphics system are designed and implemented with validation of timings and functionalities by board level simualtion. For board level simulation, models of GISC chip and components on GISC system are developed with concept of stimulus feeding system and result observing system which make simulation efficient and accurate, and make validation guaranteed. Methods to provide accurate timing parameters to the models and to analyze timing requirements are included in these concepts. Board level simulation of GISC chip and system is progressed concurrently with chip design so that it feedbacks functional and timing errors to chip designers and helps them to make perfect chip at a time as well as that perfect system can be designed before the chip is produced, which can prevent chip revision.