Design of a 5.2GHz mixed-class CMOS power amplifier for high average efficiency

Abstract

A 5.2GHz mixed-class (AB+C) CMOS power amplifier for improving efficiency at low output power region is proposed. This configuration doesn’t need any additional switches or bias control circuits for efficiency enhancement. The advantage of this configuration is only by using class C configuration and matching network. The demonstration chip is designed and simulated using Samsung 0.18um CMOS process. From simulation results using HPADS, it has been demonstrated that efficiency would be improved about 3 times at low output power region compared with conventional class AB configuration. Power amplifiers don’t transmit maximum power at all times. So it is important that efficiency in the frequent transmitted region has to be increased. So in this thesis, by improving efficiency at low output power region, we propose to enhance the average efficiency.