Characteristics of MOSFET with source/drain-to-gate non-overlapped structure

Abstract

A MOSFET structure with non-overlapped source/drain to gate region is proposed to overcome the challenges in sub-50 nm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. RF characteristics and small signal model parameters are studied with non-overlap structure with metallurgical gate length of 40 nm. The proposed structure showed good subthreshold slope and DIBL characteristics compared to those of overlapped structure.