Synthesis and verification of state machine description using automatic test vector generation

Abstract

This thesis presents an interface library manager of a behavioral emulator. The behavioral emulator is a kind of rapid pre-prototyping system that has both hardware and software part interacting with each other to emulate a specific model. This is much more speed efficient than lower level of abstraction with HDL in a simulation point of view. The interface library is a database of protocols that are used to interface between the target hardware and the behavioral part of the target chip model. In the HDL based design flow, if the designer wants to make new interface library, he has to describe it with Hardware Description Language (HDL) like verilog. It is very difficult job to study HDL. After design complete, he has to make test vector and another code for simulation. So, we set up the FSM based design flow for interface library. The designer who doesn``t know HDL can make new interface library easily. He just describes the FSM and interface specification constraints. The FSM synthesizer makes verilog code from FSM file. And the test bench generator makes simulation code with test vector from interface specification constraints. FSM based design flow is successfully applied to PCI read protocol design.