(A) new decision logic for rapid acquisition of PN sequences

Abstract

In this thesis, a fast code acquisition scheme for a direct sequence code division multiple access (DS/CDMA) system is proposed. Based on the sequential estimation scheme using a majority logic decoder, the proposed scheme adds a verifier to the majority logic decoder, improving the reliability of an initial state estimate. We drive the probability of finding a correct initial state estimate and show that the proposed scheme can reduce the average number of chips for acquisition compared with the conventional scheme in the moderate SNR region.