Design of gate-level PSG builder for behavioral emulator

Abstract

Behavioral model emulator, called iSAVE, is a kind of rapid pre-prototyping system that has both hardware and software part interacting with each other to emulate a specific model while focused on verifying the target design at the behavior or algorithm level described by high level programming language at the early stage of design. This is much more speed efficient than lower level of abstraction with HDL in a simulation point of view. For the interaction between algorithm in the behavioral emulator and target system, PSG (Pin Signal Generator) module is needed. PSG module has its control logic and user interface library logic. As control module of PSG and user interface libraries are generated by RTL level, it is necessity to re-synthesis entire PSG module in the current system. But it is very cost and time-consuming process. In this thesis, we eliminate the synthesis process of control logic and interface logic, and generate gate-level PSG core logic according to user input parameters. Then, we connect generated PSG core logic to user interface logic. As well, we solve the problem for generating gate-level PSG module.