(A) high-speed floating point divider using improved quotient selection logic in redundant binary number system

Abstract

A high-speed floating point (FP) divider using the improved quotient selection logic (QSL) realized in an overlapped parallel structure has been proposed. Generally, FP division has been regarded as a relatively infrequent, slow operation in FP arithmetic applications. However, data hazards problem becomes more serious as the clock speed becomes faster and a number of pipeline stages in modern microprocessors increases; therefore, the need for a high-speed dividers is growing. One of the methods to implement fast FP dividers is using RB number system and self-timed circuit schemes. However, the previous FP dividers implemented by using RB number system have some serious drawbacks that the QSL is very complicated and slow as a result. In this paper, a new simple and fast QSL has been proposed using divisor scaling and optimized RB addition rules and an overlapped parallel structure has been devised in order to reduce the critical path in delay. A complete FP divider has been designed, simulated, and laid out using 0.25㎛ CMOS process technology. The final post layout simulation has showed the execution time of the proposed FP divider is estimated less than 28.8 nsec for 55 bit significand floating point division, showing the performance improvement of more than 30% compared with the previous designs.