Programmable direct digital frequency synthesizer design for multi-standard receiver

Abstract

This paper describes a Programmable Direct Digital Frequency Synthesizer for multi standard receiver. The DDFS is basically based on method using ROM in this thesis. It is focused on the power consumption and spectral purity. The structure sharing the phase accumulator and divided memory structure are proposed to save hardware and power consumption. By using this structure, total power is saved by 48.4 percent. It is decreased from 40960-b to 1024-b by using the reduction methods of the ROM size. It produces 10-b sine and cosine outputs with a spurious-free dynamic range (SFDR) of more than 67.72 dBc. A 32-b frequency control word gives a frequency tuning resolution of 0.00715 Hz at the maximum clock frequency of 30.72 MHz. The DDFS was simulated with CADENCE Spectre and Verilog. The spice model parameter of the transistor used is BSIM3 based on TSMC 0.35um CMOS process. The DDFS unit block occupies 2.3 mm×1.6 mm per one channel.