Exploiting parallelism of 3D graphics geometry using a VLIW geometry processorVLIW 기하 가속기를 이용한 3차원 그래픽의 기하연산 병렬성 강화

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We use 4-way VLIW architecture called FLOVA (FLOating-point VLIW Architecture) as a geometry accelerator. And we propose three schemes to exploit the parallelism of the geometry accelerator using merits of the VLIW architecture and inherent parallelism in the 3D graphics geometry stage. In the first scheme, we find out ILP (Instruction Level Parallelism) on matrix multiplications in transformation. The second scheme, we are looking for the portions to be executed simultaneously in each pipeline stage of geometry, and it is called ALP (Algorithm Level Parallelism). The third scheme is communication overhead reduction by reformatting the data structure of the FGA``s context and vertex buffer. Therefore, the geometry accelerator using VLIW can improve a half and two times of the total graphics performance, and exploiting parallelism by ILP and ALP is cost effective solution with in the VLIW geometry accelerator.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2000
Identifier
157479/325007 / 000983458
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2000.2, [ iv, 49 p. ]

Keywords

ALP; Geometry accelerator; VLIW; Algorithm level parallelism; 명령어 레벨 병렬성; 알고리즘 레벨 병렬성; 기하연산 가속기; ILP

URI
http://hdl.handle.net/10203/37320
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=157479&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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