Implementation of hardware for behavioral model emulator

Abstract

This thesis describes a design and implementation of the hardware to verify a algorithm usually programmed in C on a real target system at early design stage. Using this system, designers can obtain a prototype of the ASIC much earlier, which significantly reduces the design time and cost. This hardware is a customized PC motherboard including components for supporting emulation features. This system is composed of a high-performance processor executing behavioral model of a target chip, DRAM storing behavioral model and FPGA generating pin signals. As an example, MP3 decoder chip is emulated to validate performance of this system, and it shows successful operation when plugged in the MP3 player board.