$.8 \um m$ CMOS를 이용한 1.485 Gb/s 병렬화기의 설계1.485 Gb/s deserializer chip design using $.8 \um m$ CMOS for HDTV application
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 조규형 | - |
| dc.contributor.advisor | Cho, Gyu-Hyeong | - |
| dc.contributor.author | 류지열 | - |
| dc.contributor.author | Ryoo, Ji-Yeoul | - |
| dc.date.accessioned | 2011-12-14T01:43:47Z | - |
| dc.date.available | 2011-12-14T01:43:47Z | - |
| dc.date.issued | 1999 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=150851&flag=dissertation | - |
| dc.identifier.uri | http://hdl.handle.net/10203/37162 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1999.2, [ vi, 78 p. ] | - |
| dc.language | kor | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | 디멀티플렉서 | - |
| dc.subject | 쿼더리코릴레이터 | - |
| dc.subject | 피엘엘 | - |
| dc.subject | 병렬화기 | - |
| dc.subject | 고해상도 티브이 | - |
| dc.subject | 루프이득조절 | - |
| dc.subject | Loop gain control | - |
| dc.subject | Demultiplexer | - |
| dc.subject | Quadricorrelator | - |
| dc.subject | PLL | - |
| dc.subject | Deserializer | - |
| dc.subject | HDTV | - |
| dc.title | $.8 \um m$ CMOS를 이용한 1.485 Gb/s 병렬화기의 설계 | - |
| dc.title.alternative | 1.485 Gb/s deserializer chip design using $.8 \um m$ CMOS for HDTV application | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 150851/325007 | - |
| dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
| dc.identifier.uid | 000973233 | - |
| dc.contributor.localauthor | 조규형 | - |
| dc.contributor.localauthor | Cho, Gyu-Hyeong | - |
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- EE-Theses_Master(석사논문)
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