(A) datapath layout generator for microprocessors

Abstract

This thesis describes a datapath layout generator which makes a regularly structured datapath layout for microprocessors. The datapath layout generator takes a netlist and cell ordering information as input, and generates a layout for the datapath module. It works for three-layer-metal technology, and uses two metal layers for bus and inter-bitslice routing. To reduce the channel density, first it routes most of bus connections using the second metal layer, and then it performs the over-the-cell routing using the third metal layer for the remained buses. The channel routing algorithm is mainly based on the left-edge channel routing algorithm. But to reduce inter-bitslice routing channels, a new strategy is presented. After inter-bitslice routing tracks are assigned, it builds a constraint graph. Taking this graph into account, finally it performs bus routing. The proposed scheme is valuable in reducing the width of a datapath layout. This datapath layout generator is programmed in SKILL language provided by Cadence Design Systems, Inc.