Investigation on resistive switching transistor operation and memory application

Abstract

A resistive switching transistor (REST) structure is proposed for size reduction and low power operation of memory cell. The proposed structure is composed of a Ti gate interfaced with bi-layer gate dielectric, ZnO at a gate side and $SiO_2$ at a channel side, and a silicon channel with a source and drain. $Ti/TiO_2$ interface can be formed with annealing process on Ti/ZnO interface. The $Ti/TiO_2$ interface in the gate shows resistive switching and it leads to modulate threshold voltage. Particularly, resistive switching is enabled even at extremely low current flow due to the existence of the thin SiO2. Thus REST is attractive in aspect of low power memory operation.