Low Cost wafer-level packaging method based on anodized aluminum substrate with backside signal Pad and EMC passivation

Abstract

This thesis studies the package methodology in Wafer-Level Package (WLP) and Multi-Chip Module-Deposition (MCM-D) for RF applications. The study is focused in anodized aluminum substrate, suitable for manufacture cost reduction. The advantages of this package type are that it does not require additional wire bonding or solder bumping techniques. The fabricated chip is mounted on circuit board by conductive epoxy, similar to surface mount device. Also the passivation of epoxy molding compound (EMC) provide additional protection to the chip. A fabrication process was developed which is quite straight forward, compared to Si or 3-5 group compound substrates. All the fabrication process was conducted in semiconductor process, guaranteeing high integration density. The fabrication process is described in detail in chapter 3, including the circuit fabrication process and package process. Also, an effective equivalent circuit model was established in lumped elements for future designs. EM geometrical simulations were performed for confirmation. The previous modeling method is explained in chapter 4. The circuit model was verified by experimental measurements in chapter 5 and a balun also acting as a band pass filter was fabricated base on the proposed package method and the results were discussed in chapter 6.