Reduction of parasitic capacitance in heterojunction bipolar transistor and its monolithic integration with field effect transistor이종접합 바이폴라 트랜지스터의 성능향상과 전계효과 트랜지스터와의 집적에 관한 연구

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dc.contributor.advisorKwon, Young-Se-
dc.contributor.advisor권영세-
dc.contributor.authorShin, Hyun-Chol-
dc.contributor.author신현철-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued1998-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=135252&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36449-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1998.2, [ 113 p. ]-
dc.languageeng-
dc.publisher한국과학기술원-
dc.titleReduction of parasitic capacitance in heterojunction bipolar transistor and its monolithic integration with field effect transistor-
dc.title.alternative이종접합 바이폴라 트랜지스터의 성능향상과 전계효과 트랜지스터와의 집적에 관한 연구-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN135252/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000935201-
dc.contributor.localauthorKwon, Young-Se-
dc.contributor.localauthor권영세-
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EE-Theses_Ph.D.(박사논문)
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