Analysis and design of 2.3-GHz current-controlled oscillator using novel multiple-nested ring architecture and a 2-GHz PLL frequency synthesizer design새로운 다중 연결 링 구조를 이용한 2.3-GHz 전류 제어 발진기의 해석과 설계 및 2-GHz PLL 주파수 합성기의 설계

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A novel differential voltage-clamped current-mode delay cell is proposed and its advantages such as low supply sensitivity, wide tuning range and high speed operation are verified by a three-stage ring oscillator through fabrication and experiments. Due to the nature of current mode with voltage clamping and robustness against noise, experimental results show the supply sensitivity is very low about 0.1~0.2 %/V in the 500 ~ 800 MHz range having its tuning range over 1 decade up to 1.38 GHz. Based on the differential voltage-clamped current-mode delay cell, the novel multiple-nested ring (MNR) oscillator architectures are developed and four types of MNR oscillators are presented. Among them, two MNR oscillators are implemented using a 0.8 ($\mu$ nwell CMOS process. Since the operation of their delay cells is basically a voltage-clamped and current-mode, the experimental verifications of two MNR oscillators show such properties as wide tuning range, low supply sensitivity and high speed operation. Using the feedback theory, the loop gain analyses for the four types of MNR oscillators and conventional three- and four-stage ring oscillators are carried out. From the loop gain analyses, the oscillator characteristic parameters such as the oscillation frequency and minimum gain for oscillation are obtained for each type of oscillators. Throughout the analyses, we find that the oscillation frequencies of MNR oscillators can be made higher than those of conventional ring oscillators and obtain the functions which show ``how much the oscillation frequencies of MNR oscillators can be increased compared with those of conventional ring oscillators``. The noise analyses of MNR oscillators for the noise performance parameters such as thermal output noise power of the delay cell, noise spectral density function and total output noise power are performed. From these analyses, we obtain the functions which show ``how much the noise performance of MNR oscillators can be...
Advisors
Cho, Gyu-Hyeongresearcher조규형researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1997
Identifier
128041/325007 / 000925575
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1997.8, [ xxiv, 303 p. ]

Keywords

High-speed current-driven prescaler; Multiple-nested ring oscillator; High-speed voltage-clamped current-mode ring osillator; Frequency synthesizer; 주파수 합성기; 고속 전류구동 프리스케일러; 다중연결 링 발진기; 고속 전압클램트된 전류모드 발진기

URI
http://hdl.handle.net/10203/36391
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=128041&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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