Area and power minimization in controller synthesis제어기 합성에서의 면적과 파워의 최소화

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dc.contributor.advisorKyung, Chong-Min-
dc.contributor.advisor경종민-
dc.contributor.authorHong, Se-Kyoung-
dc.contributor.author홍세경-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued1995-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=99152&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36278-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1995.2, [ vi, 104 p. ]-
dc.description.abstractThe design of control unit in VLSI requires careful attention. It must guarantee maximal performance of the data path. Also it should not require excessive area nor introduce critical paths. But current VLSI technology made designers difficult to optimize the cost functions at hand because of the increase in the level of integration. In this thesis, algorithmic methods which can optimize objective functions of control units such as power and area are addressed. In chapter 2, the problem of minimizing the control store width is addressed. It is very important in the design of microprogrammed processors, because it is directly related to the silicon area of control unit. For the minimization of the control store width three approaches are presented. The first two methods target minimal encoding scheme. One of them uses integer linear programming formulation by representing the cost function in linear form. It gives optimal solutions for only small-sized problems. The other is a heuristic approach using the graph partitioning algorithm. The minimal encoding scheme is modeled by graph partitioning problem. This approach gives nearly optimal solutions with the reasonable amount of time. And the last approach is based on the notion of minimal dependence sets. The problem can be transformed into the minimal column covering. An heuristic method for minimal column covering is given. The experimental results show that this method is efficient for highly parallel microcode. In chapter 3, a state assignment algorithm of Finite State Machines for minimal switching power consumption is proposed. Low power is essential due to not only packaging and cooling costs but also lifetime of integrated circuits and batteries. The proposed algorithm minimizes the switching activity caused by state transitions by assigning codes closer in Hamming distance to the states with higher state transition probabilities. First, the proposed algorithm calculates the state transition probabilities...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.titleArea and power minimization in controller synthesis-
dc.title.alternative제어기 합성에서의 면적과 파워의 최소화-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN99152/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000885537-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.localauthor경종민-
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EE-Theses_Ph.D.(박사논문)
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