(A) study on the optimization of CMOS buffer circuit

Abstract

Power consumption has risen as a main concern for electronic devices. The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of power-delay product, i.e. switching energy. In case of uniform tapering, we can obtain an analytical solution of the tapering factor for the minimum power-delay product, which is about 1.5-2 times larger than that for the minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for the minimum power-delay product, which, however, results in larger short-circuit current. This buffer design optimized for switching energy saves 15-35% energy compared with that optimized for minimum delay. Compared with uniform tapered buffer, nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3-5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE. The effect of the size ratio of PMOS to NMOS and power supply voltage scaling upon the power-delay product of the buffer is analyzed. Area optimization and integer nature of the number of stage in buffer circuit is also considered. Finally, full custom optimum buffer module generator is implemented for a various given criteria and design options, such as a propagation delay, power consumption, area, and power-delay product. This generator gives much better versatility in designing tapered buffer circuits.