Asynchronous transfer mode (ATM) has been widely accepted as the most promising solution to implement the broadband ISDN. But, since ATM is based on the use of very high-speed and reliable fiber optic transmission facilities, it has been very important issue to design a high-performance packet switch to meet the throughput requirements. Thus, various architectures for ATM switches have been proposed, and many of the proposed switching architectures employ the banyan network as a basic building block because of its hardware simplicity and selfrouting capability. In this dissertation work, we study the cut-through buffered banyan and the dilated banyan networks for ATM switch design. First, we present an analytic model for estimating the performance of buffered banyan networks with cut-through. In the analytic model, we assume that the input traffic is uniform and consider throughput and delay as relevant performance measures. In order to consider the dependencies between consecutive time slots, we first analyze two head-of-line (HOL) buffers of a switching element (SE) by introducing the "blocked" state, and then analyze the whole buffer module in the SE with a Markov chain. To validate the analytic model, we compare some analytic results to simulation results. The comparison shows that the analytic results appear to be in good agreement with simulation for light and medium loads, but have small difference from simulation results at heavy load. Next, we propose a dilated banyan network with back-pressure mechanism to fully utilize the routing capacity wasted in a pure dilated banyan network. The proposed switch has both input and output queues, and employs a priority scheme in order to prevent the out-of-sequence problem. We also design the nonblocking SE which is constructed using two sorting networks and a routing stage, in order to reduce the hardware complexity of the dilated network. The performance of the proposed switch is analyzed under the uniform traff...