Two heutistic algotithms for integrated circuitlayout

Abstract

This thesis introduces two heuristic algorithms for layout generation, which consists of two parts. In the first part, a three-step heuristic algorithm for PLA column folding and row folding of column-folded PLA is presented. The three steps are i) Min-Cut partition of vertices in the column(or row) intersection graph, ii) determination of products order using Fiduccia``s Min-Net Cut algorithm, and iii) head tail pairing for column folding, while some heuristics are proposed for deciding row folding pairs. For test PLA``s, the proposed algorithm is significantly faster than the earlier works and provides nearly optimal results. In the second part, an efficient heuristic algorithm for the placement of standard cells in a rectangular or rectilinear region using successive alternating-direction ordering (SADO) is proposed, which is fast and provides good results. An advantage of the proposed algorithm is that, compared to the Min-Cut placement which only minimizes the number of nets when the cells are partitioned into two, this algorithm partitions the cells with the consideration of the potential location of each cell from the very beginning. Successive cell-ordering and bi-partitioning method coupled with a slicing structure determines the positions of the cells hierarchically, which removes the greedy nature of the greedy clustering approach in positioning the cells. The computational complexity of the algorithm is proven to be $O(n(logn)^2)$. for test circuits, the measured costs, the number of routing tracks or the half-perimeter routing length, were smaller than those of the other algorithms.