Accelerating multimedia applications with a reconfigurable system

Abstract

The verification time has become the most important issue on the de-signing a chip, especially on implementing an algorithm which requires large computation capacity, such like multimedia, on a chip. This pa-per is consisted of two parts: at first, the reconfigurable system which enables the algorithm runs with a target board and development environment which synthesize codes to connect the algorithm and interfaces of chips are introduced. The second one is the cosimulation environment within which the algorithm partitioned to hardware and software are verified step by step. The embedded software is executed on native machine-code level, instead of simulation on ISS(Instruction Set Simulator), while estimating cycle counts and synchronizing with the hardware models at basic block boundary. The proposed idea is validated by emulating a MP3 decoder chip with a public domain MP3 program and by simulating software and hardware models of the chip together with the proposed simulation environment.