DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, In-Cheol | - |
dc.contributor.advisor | 박인철 | - |
dc.contributor.author | Lee, Jong-Yeol | - |
dc.contributor.author | 이종열 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2002 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=177322&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36027 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.8, [ xi, 126 p. ] | - |
dc.description.abstract | A system-on-chip (SOC) is a complex integrated circuit that encompasses functional elements including software modules and hardware components. SOCs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and consumer electronics. For the design of SOCs, methods of compiling embedded software and automatically generating synthesizable hardware description from high-level language description are presented in the thesis. A new simulation method that can be used in analyzing the performance of SOCs is also presented. Firstly, this thesis presents a new code optimization method for embedded digital signal processors. In the proposed code optimization method, the special architectural features of embedded digital signal processors such as address generation units and hardware loop instructions are exploited. The proposed method employs a high-level transformation and a new graph representation called value-trace graph to fully utilize the special features. The thesis also proposes a hardware design method in which synthesizable hardware description is generated from high-level programming language description. In the proposed method, in order to reveal the parallelism between modules, global variables are localized since the global variables in high-level language description cause dependency relations between hardware modules. Lastly, a new simulation method called timed compiled-code functional simulation is proposed in the thesis. The timed compiled-code functional simulation, which is proposed for the performance analysis of SOC designs, simulates the whole design at a functional level with timing. A fast and accurate performance analysis is greatly required in designing SOCs because parts of the SOC development process will require the ability to rapidly assemble accurate performance estimators to provide feedback during system-level optimization. As SOCs include software components as well as hardware modules, the ti... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Compiled-Code SImulation | - |
dc.subject | code optimization | - |
dc.subject | 컴파일 코드 방식 | - |
dc.subject | 시뮬레이션 | - |
dc.subject | 코드 최적화 | - |
dc.subject | Compiled-Code SImulation | - |
dc.subject | code optimization | - |
dc.subject | 컴파일 코드 방식 | - |
dc.subject | 시뮬레이션 | - |
dc.subject | 코드 최적화 | - |
dc.title | Timed compiled-code simulation and code optimization for embedded software | - |
dc.title.alternative | 내장형 소프트웨어를 위한 컴파일 코드 방식의 시뮬레이션과 코드 최적화 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 177322/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000965303 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.localauthor | 박인철 | - |
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