Low-noise PLL/DLL design and jitter/phase noise analysis

Abstract

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the phase-locked loop increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward type duty cycle corrector is designed to keep the 50-\% duty cycle ratio over all operating frequency range. In this paper, a wide-locking range, low jitter delay-locked loop (DLL) is also presented. Since a relatively delay-changing delay cell is used as a unit cell of a voltage-controlled delay line (VCDL), it has a wide operating input frequency range and, at the same time, achieves low jitter. The DLL is fabricated with sige5am Vi.i of the IBM SiGe process. The simulated locking time is less than 400 ns and the PSS simulation results show the estimated cycle-to-cycle jitter is less than 1 ps By applying a cyclo-stationary concept to oscillating signals, an analytical relation between phase noise and jitter is also derived in this paper.