DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Beom-Sup | - |
dc.contributor.advisor | 김범섭 | - |
dc.contributor.author | Yang, Jeong-Sik | - |
dc.contributor.author | 양정식 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2002 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174616&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35983 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ vii, 92 p. ] | - |
dc.description.abstract | High bandwidth data transmission is necessary for increasing the performance of the digital systems. However, it is not easy to achieve because of many limiting factors like signal integrity, propagation delay, clock-data skew and jitter, etc. This paper investigates the advantages and disadvantages of the conventional interfaces and proposes new design techniques for increasing the data transmission rate. Signal integrity is one of the main issues arising in data transmission. It is affected by many problems like limited channel bandwidth, reflection, and ringing, etc. To alleviate these problems, this paper adopts a high-speed data transceiver comprising a multiplexing transmitter with pre-emphasis, an analog adaptive equalizer and high-speed data latch with automatic power saving circuit. Because the pre-emphasis and adaptive equalization completely compensate the effect of the band-limited channel, this transceiver can achieve wider eye opening and higher signal-to-noise ratio. And proposed data latch can save power without speed degradation. Another main issues are clock generation and synchronization between data and clock. This paper proposes a global synchronization technique for bus topology and a delay insensitive timing recovery technique for point-to-point topology respectively. The global synchronization technique for bus topology comprises a global synchronous clock circuitry and a pin-to-pin skew compensation circuitry. The global synchronous clock circuitry uses the forward direction clock (FDCLK) and backward direction clock (BDCLK) signals to derive the global synchronous clock signal, which is synchronous throughout the system. The pin-to-pin skew compensation circuitry minimizes the clock-data skew to avoid errors. The delay insensitive timing recovery technique for point-to-point topology uses new algorithm to reduce the effect of the delay between data sampling and timing update. It can provide accurate timing to the data sampler. To p... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Global Synchronization Circuitry | - |
dc.subject | Delay Insensitive Timing Recovery Algorithm | - |
dc.subject | Analog Adaptive Equalizer | - |
dc.subject | High Speed Interface | - |
dc.subject | Multi-phase Clock Generator | - |
dc.subject | 다위상 클럭 발생기 | - |
dc.subject | 공통 동기화 회로 | - |
dc.subject | 지연에 둔감한 타이밍 복원 알고리즘 | - |
dc.subject | 아날로그 적응 이퀄라이저 | - |
dc.subject | 고속 인터페이스 | - |
dc.title | High speed interfaces for chip-to-chip communication | - |
dc.title.alternative | 칩간 통신을 위한 고속 인터페이스 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 174616/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000965229 | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.localauthor | 김범섭 | - |
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