Scalable parallel rendering architecture using interleaved scanline rasterization확장 가능한 주사선 할당 방식의 병렬 렌더링 시스템 구현

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dc.contributor.advisorPark, Kyu-Ho-
dc.contributor.advisor박규호-
dc.contributor.authorKim, Jun-Sung-
dc.contributor.author김준성-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2001-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169551&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35950-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ xii, 142 p. ]-
dc.description.abstractThe 3D computer graphics becomes the most important tool for the scientific visualization and military simulation, as well as the inevitable medium for personal communications. Although the computing technology has been improved, the current demand toward higher quality in real-time applications is beyond the performance of existing graphics computers. To improve rendering performance, many researchers have devoted their efforts to the development of parallelization methods, dedicated processing elements, and special memory-processor organization. And this thesis, as one of such efforts, makes a contribution to the development of graphics computers by introducing new ideas for parallel rendering architecture. A scalable parallel rendering architecture based on the interleaved scanline rasterization is presented, which successfully removes the sorting overhead resident in the conventional scanline-based parallel rendering. Nevertheless, all advantageous features of the scanline-based rendering are kept; The frame memory bottleneck does not exist; The clipping overhead and the load imbalance shown in other region-based rendering approaches do not appear; The memory requirement is constant regardless to the number of rasterizers. The performance of the proposed architecture is evaluated by discrete event-based hardware simulator (DEVHS). which is made for combinational circuit modeling and simulation purpose. As expected, a good scalability is shown under the limitation of the polygon bus. More than 8 Mtriangles/s performance of PC-based rendering system is expected using 64 rasterizers and the AGP 2x bus. The first prototyping of rasterization board have been implemented and its functional verification is finished. Communication overhead is also a major issue in parallel rendering architecture. By making use of the fact that the vertical motion of objects in computer animation is very smooth, the proposed primitive distribution algorithms effectively reduce net...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectcomputer graphics-
dc.subjectrendering-
dc.subject렌더링-
dc.subject컴퓨터 그래픽스-
dc.titleScalable parallel rendering architecture using interleaved scanline rasterization-
dc.title.alternative확장 가능한 주사선 할당 방식의 병렬 렌더링 시스템 구현-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN169551/325007-
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid000955084-
dc.contributor.localauthorPark, Kyu-Ho-
dc.contributor.localauthor박규호-
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