(A) DLL-based frequency synthesizer with selective reuse of a delay cell scheme for 2.4 GHz ISM band

Abstract

For the design of communications circuits, the ultimate goal is to implement a single chip transceiver with the minimum number of off-chip components. A high level of integration enables significant cost and size reduction. However, for a cost-effective CMOS process, one of the most challenging parts of transceiver integration is the realization of low phase noise synthesizers with low-Q on-chip components. One approach overcoming the limitation is to use an LC-tank voltage controlled oscillator (VCO) with a Q-enhancing technique for the inductor [1]. Another approach is to use a delay-locked loop (DLL) and a frequency multiplier with an edge combiner [2]. The phase noise is improved because no timing jitter is accumulated from cycle to cycle when DLLs are used. However, the number of delay cells determines the multiplication factor and the multiplication factor is fixed. Consequently, the latter method has limitations whenever a variable or a large multiplication factor is required. This paper presents a DLL-based frequency synthesizer that selectively reuses a delay cell. By switching the number of delay cells that a signal goes through in a proper sequence, the frequency synthesizer can generate multiple frequency output with a small number of delay cells. With only 9 delay cells, the test chip achieves frequency multiplication factors greater than 240. It also provides multiple frequency output by adjusting the multiplication factor similarly to a conventional frequency synthesizer. This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) compa...