Interface synthesis methods for a heterogeneous chip area network

Abstract

Systems are moving fast toward chip-level implementations that can be modeled as a heterogeneous network of communicating chip-level components, which we call a heterogeneous chip area network (HCAN). As the complexity and time-to-market pressure of systems increase, new design methods are required. In this dissertation, we propose interface synthesis methods for a heterogeneous chip area network. Since the input to our methods is interface specification of components, we proposed a new formal model of interface that abstracts well the characteristics of a component protocol. Using the input specifications, communication channels must be constructed for every matched pair of communicating atomic protocols. The interface architecture for those communication channels is determined to support fast communication among components. If two communicating protocols are incompatible, a converter must be provided. Although many protocols in use are nonblocking protocols or blocking protocols whose blocking period is limited, previous studies required both the input protocols to their protocol converter must be blocking protocols with a unlimited blocking period. Our protocol conversion supports nonblocking protocols and blocking protocols with a limited blocking period. The result widens the application of protocol converters. The proposed methods enable us to compose a complex system with existing components without modifying the interface of those components, thereby enhance the productivity of designing complex heterogeneous chip area networks. For interface implementation, recently low power interface is much concerned. We propose a {\it mesochronous} bus, whose bus lines have non-overlapping bus transitions in every clock cycle, to reduce the peak I/O power dissipation. Its experimental results with 0.18$\mu$m libraries outperform the results of previous work for a wide range of bus frequencies. We also present a method to reduce power d...