Synthesis of application specific instructions for embedded DSP software

Abstract

Application specific instruction-set processor (ASIP) becomes more and more important in the design of complex embedded DSP systems due to its programmability and its increasing performance. Choosing an optimal instruction-set for the specific application under the constraints such as chip area and power consumption is most crucial in enhancing the performance of the ASIP. However, recent trends in design, i.e., starting from the high-level description of a system and extensive reuse of complex building blocks, have made the task very hard for designers. Hence, in this thesis we propose new automatic ways to generate the optimal instruction-set for the ASIP composed of a processor-core and several hardware accelerators from a given application program written in C-language. First, the generation of application specific instructions to be run in the processor-core is handled. It is based on a modified subset-sum problem, and supports multi-cycle instructions as well as single-cycle instructions, while the previous approaches generate only the single-cycle instructions. Second, we handle the generation of instructions using pre-designed special hardware accelerators, i.e., intellectual properties (IP``s). The proposed approach selects IP``s with considering interfaces and supports concurrent execution of processor-core with IP``s, which are not possible in the previous methods. Lastly, we propose a new pipelining technique, called coware pipelining, to use IP``s more efficiently in the generation of instructions. The proposed approach can increase parallelism among tasks significantly over the original one and can lead to better use of IP``s, whereas the previous approaches can exploit only the original parallelism in the application program. The experimental results on real applications showing the efficiency of the proposed methods are also included.