Design and performance analysis of asynchronous switches비동기 스위치의 설계 및 성능 분석에 관한 연구

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The main objective of this dissertation work is to design switch architectures for broadband packet networks and to analyze their performances. First, we propose an architecture of the asynchronous non-blocking switch. The switch structure is relatively simple, but it has an advantage in that a window scheme can easily be implemented. Many switch structures synchronized with time slots have been proposed, but they are not good for implementing a window scheme. The asynchronous switch with its implementation of a window scheme can increase its maximum throughput up to 1 in the case of minimum change-over time and large packet size. We also investigate the delay characteristics of the asynchronous switch. In the analysis of the delay characteristics, we make some approximations. But the results of the analysis show good agreements with simulation results. In addition, the maximum throughput of the switch with finite window size is investigated. Next, we propose a structure of the asynchronous banyan network switch with a window scheme. The switch operates asynchronously, and thus it can transmit packets of any length at any bit time. When a packet has a collision inside the switch and is blocks, the failure signal is transferred to the input controller which originated the packet. Hence there is no loss of packets in the switch. The switch has a significant advantage in that a window scheme can be implemented. The asynchronous switch with a window scheme yields significant improvement of the maximum throughout as compared to the synchronous banyan network with no window scheme. We analyze the maximum throughput of the asychronous switch with infinite window size and finite window size, respectively. The results of the analysis show good agreements with the simulation results. Finally, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the pri...
Advisors
Un, Chong-Kwanresearcher은종관researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1993
Identifier
60584/325007 / 000865290
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1993.2, [ v, 178 p. ]

URI
http://hdl.handle.net/10203/35707
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=60584&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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