Automatic sizing algorithm for CMOS combinational circuits

Abstract

An algorithm for automatic and heuristic sizing for CMOS combinational circuits is proposed. The three design objectives-area, delay, and product of the area and delay with weight-are formulated. By selecting the objective, designer can adjust the performance of a circuit without simulation. Area and fanout load capacitance are estimated accurately using a template layout for basic logic gates. A semi-empirical delay model for an inverter considering the actual slope of input waveforms, a load capacitance, and channel width of transistor is presented and gives an accurate delay value. Gate-based optimization is adopted here to reduce the size of problem space for optimizer, to the number of gates instead of the number of transistors. The sizing problem in general logic can be handled as inverter case by normalizing the effective width of transistor in general logic to width in inverter. The selection strategy for design variables is to give an equal opportunity to each gate to be optimized. The amount of size modification per each gate is determined by mathematical optimizer depending of the improvement for a design objective function. Therefore, the entire circuit is opatimized at the same time and a global solution in the circuit is sought. The mathematical optimization method by Rosenbrock is modified and characterized for our problem. The optimizer seeks an optimal solution of a design objective function while varying the size of design variables. The algorithm for automatic sizing is implemented in Optsizer program. By running Optsizer on four stage optimization problem, we have a good solution such that both area and stages of inverter is optimized, a lifting phenomena of size at earlier stages is occurred. The sizing result using the lifting phenomena gives a better solution rather than using the tapering factor of logarithm, e.