Flash translation layer for NAND flash memory based SSDs with configurable mapping and adaptive merge scheme

Abstract

The Flash translation layer (FTL) in solid state disks (SSDs) maps logical addresses to physical addresses for disk drive virtualization. In order to reduce the mapping table size, hybrid FTLs for SSDs are used with block-level mapping for data blocks and page-level mapping for log blocks. Obsolete blocks are reclaimed by garbage collection, which reconstructs data blocks by merging data blocks and log blocks. In this case, because of the large-sized mapping level and low log block utilization, garbage collection overhead becomes the bottleneck on fragmented writes. In order to reduce garbage collection overhead, we propose full-associative striped block-level mapping. In addition, an adaptive merge is proposed to avoid excessive data block reconstructions during garbage collection. Our proposed FTL achieves load-balancing, since it allocates and erases blocks in a round-robin manner. We investigate the performance of the proposed FTL with previous multi-channel hybrid FTLs by a trace driven simulator. Our FTL provides 78% latency improvement over the previous hybrid FTLs in a sample PC trace. The performance improvements stem from 52% reduced garbage collection. We also achieve load-balancing within 0.15% write/erase operation deviation over multiple modules on 20% skewed logical address accesses.