Flash memory utilizing discrete charge storage node for universal memory이산적 전하 저장소가 삽입된 플래시 메모리 및 Universal 메모리로의 응용

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dc.contributor.advisorChoi, Yang -Kyu-
dc.contributor.advisor최양규-
dc.contributor.authorRyu, Seong-Wan-
dc.contributor.author류승완-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2009-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=327773&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35540-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009. 8., [ iv, 146 p. ]-
dc.description.abstractThe development of silicon technology faces new paradigm of the universal memory for high performance and multi-functioning rather than the scalability issue in the digital convergence era. It stems from the demands of the multifunctional device integration for the system-on-chip (SoC) technology and multi-chip-package (MCP) application. As an emerging device, if high speed of dynamic-random-access-memory (DRAM) and nonvolatibility of Flash memory are implemented in a single cell, the multifunctional devices can have more strength in highly efficient data storage than SoC and MCP, which includes both a customized intrinsic NVM part and a DRAM part due to the aforementioned reasons. A unified random-access-memory (URAM) concept is proposed by considering aforementioned requirements. This thesis is largely categorized for two parts of the planar and 3-dimensional URAMs. And, for each part, each memory operation of the NVM and DRAM is optimized for the performance enhancement. The first part of the NVM operation of the planar URAM addresses the floating gate engineering through high gate capacitive coupling ratio of nanocrystal (NC) geometry modulation and standing single-wall carbon nanotubes. High aspect ratio of the floating gate nodes provides more program efficiency without sacrifice of reliability stability. Furthermore, in the double-stacked NC (DSNC) layer configuration doubling the NC density, the best combination is investigated for the workfunction (WF) engineered DSNCs composed with different top and bottom NC materials. The DSNC device combined top high and bottom low WF NC layers give the superior memory performance in terms of program efficiency and retention time characteristics among four types. These NVM concepts are implemented on the silicon-on-insulator and 1 transistor (T)-DRAM operation is demonstrated to utilize the floating body as a charge storage node for the accumulated holes by impact ionization mechanism. Thus, the URAM concept as ...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectUniversal Memory-
dc.subjectURAM-
dc.subjectDRAM-
dc.subjectFlash Memory-
dc.subjectNanocrystal-
dc.subjectUniversal 메모리-
dc.subject융합메모리-
dc.subject디램-
dc.subject플래쉬 메모리-
dc.subject나노입자-
dc.subjectUniversal Memory-
dc.subjectURAM-
dc.subjectDRAM-
dc.subjectFlash Memory-
dc.subjectNanocrystal-
dc.subjectUniversal 메모리-
dc.subject융합메모리-
dc.subject디램-
dc.subject플래쉬 메모리-
dc.subject나노입자-
dc.titleFlash memory utilizing discrete charge storage node for universal memory-
dc.title.alternative이산적 전하 저장소가 삽입된 플래시 메모리 및 Universal 메모리로의 응용-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN327773/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020047193-
dc.contributor.localauthorChoi, Yang -Kyu-
dc.contributor.localauthor최양규-
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