Direct-conversion receiver and transmitter for cellular CDMA and PCS applications

Abstract

A high $IIP_2$ direct conversion receiver for Cellular CDMA/PCS/GPS applications is presented. The developed two-chip solution achieves very high $IIP_2$ and $IIP_3$ with low overall noise figure. For high $IIP_2$ performance, an even-harmonic reduction technique is introduced based on a simplified analysis of second-order intermodulation. This proposed technique reduces receiver $IIP_2$ sensitivity to operating conditions and load mismatches for $IIP_2$ improvement. This thesis presents a 0.35um BiCMOS direct conversion transmitter IC with a fractional-N frequency synthesizer using a wideband VCO and a fast automatic frequency calibration (AFC) technique for CDMA applications. The developed transmitter IC achieves the lowest power consumption compared with other published and commercial products by fully integrating fractional-N frequency synthesizer and VCO, optimizing the signal processing block current over full dynamic range, and reducing the switching time using the proposed N-target algorithm. This thesis presents the principles and technique for achieving a transmitter with low power consumption. Our technique involves simple LO architecture and effective elimination of the VCO remodulation by the harmonics of the output signals.