Design of high-performance and low-cost channel in high-speed serial link고속 직렬 링크 내 저가형 고성능 채널 설계

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dc.contributor.advisorKim, Joung-Ho-
dc.contributor.advisor김정호-
dc.contributor.authorKam, Dong-Gun-
dc.contributor.author감동근-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2006-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=310363&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35522-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.8, [ xi, 136 p. ]-
dc.description.abstractProcessors’ increasing computational capability is driving a need for high-speed links to communicate the processed information. Today’s internal circuits can run at tens of gigabits per second (Gbps), but the bandwidth of the channel limits link performance. Among channel components, the package is becoming a major bandwidth restraint. Wire-bonded plastic ball grid array (WB-PBGA) is the most popular package for cost-effective conventional mid-speed applications. Previous work has studied the use of WB-PBGA packages for up to 10-Gbps data rates. As data rates continue to increase, transitioning to flip-chip interconnects or low-loss substrate materials results in excessive cost. It is therefore increasingly important to provide a high-performance and low-cost packaging solution. This dissertation presents a 40-Gbps packaging solution that uses low-cost WB-PBGA technology. Since such a high speed is beyond the reach of conventional package design, new design methodologies are proposed, including discontinuity cancellation in signal-current paths and the supply of low-inductance return-current paths. The design methods of bonding wires, vias, ball pads, and power distribution networks are suggested. The effect of each design method is examined quantitatively by both simulation and measurement. Two versions of four-layer WB-PBGA packages are designed, one according to the proposed methodologies, and the other conventionally. The proposed packaging solution is verified with both frequency-domain measurement and time-domain measurement. The conventional design’s insertion loss is measured above 10 dB at 30 GHz. A resonance occurs even at around at 23 GHz, where the insertion loss increases up to 15 dB. However, the proposed design’s insertion loss is below 3.5 dB at up to 30 GHz, and the 3-dB frequency is higher than 20 GHz. Furthermore, there is no resonance, meaning that the signal does not feel any severe discontinuity when passing through the package. Mea...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectball grid array (BGA)-
dc.subjectwire bonding-
dc.subjectvia-
dc.subjectball pad-
dc.subjectpower distribution network (PDN)-
dc.subjectreturn current path-
dc.subjectdiscontinuity cancellation-
dc.subjecthigh-speed serial link-
dc.subject볼그리드어레이-
dc.subject와이어본딩-
dc.subject비아-
dc.subject볼패드-
dc.subject전력/접지 공급 망-
dc.subject회귀 전류 경로-
dc.subject불연속 해소-
dc.subject고속 직렬 링크-
dc.subjectball grid array (BGA)-
dc.subjectwire bonding-
dc.subjectvia-
dc.subjectball pad-
dc.subjectpower distribution network (PDN)-
dc.subjectreturn current path-
dc.subjectdiscontinuity cancellation-
dc.subjecthigh-speed serial link-
dc.subject볼그리드어레이-
dc.subject와이어본딩-
dc.subject비아-
dc.subject볼패드-
dc.subject전력/접지 공급 망-
dc.subject회귀 전류 경로-
dc.subject불연속 해소-
dc.subject고속 직렬 링크-
dc.titleDesign of high-performance and low-cost channel in high-speed serial link-
dc.title.alternative고속 직렬 링크 내 저가형 고성능 채널 설계-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN310363/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020025001-
dc.contributor.localauthorKim, Joung-Ho-
dc.contributor.localauthor김정호-
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EE-Theses_Ph.D.(박사논문)
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