Speculative loop pipelining in automatic binary translation for hardware acceleration = 하드웨어 가속을 위한 자동 이진 변환에서의 추론적 루프 파이프라이닝

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Advisors
Kim, Tag-Gonresearcher김탁곤researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2008
Identifier
295405/325007  / 020025181
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2008.2, [ vii, 89 p. ]

Keywords

Binary translation; loop pipelining; memory optimization; hardware acceleration; recon??gurable computing; 이진변환; 루프 파이프라이닝; 메모리 최적화; 하드웨어 가속; 재구성 컴퓨팅; Binary translation; loop pipelining; memory optimization; hardware acceleration; recon??gurable computing; 이진변환; 루프 파이프라이닝; 메모리 최적화; 하드웨어 가속; 재구성 컴퓨팅

URI
http://hdl.handle.net/10203/35445
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=295405&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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