Fabrication of Fin-FET nanocrystal memory device

Abstract

The rapid growth of the market for portable electronic appliances requires flash memory with high performance such as very large storage density, low power consumption and past operation. This high performance was achieved by device scale down. But flash memory has some limitations in device scale down. The tunnel oxide thickness has to more than 8~9 nm due to the basic operation mechanism of flash memory. Nanocrystal memory was proposed for the solution of conventional flash memory scale down limits because this device is more robust to leakage through oxide defects and then has thinner tunnel oxide about 2~3 nm thickness. But the nanocrystal memory still has MOSFET scale down limits due to short channel effects at the device size down to 50 nm. In this work, Fin-FET nanocrystal memory device was proposed having fin structure with nanocrystal inserted gate stack layer for the real scale down for nonvolatile memory in to the nano-scale era. This structure has nonvolatile memory characteristics due to the nanocrystal memory structure and short channel effect immunity due the double-gate fin structure. Silicon nanocrystal array, the key part of proposed device was prepared by a low-temperature photo-CVD technique. Si nanocrystals with a high number density and a uniform size distribution were successfully fabricated on a $SiO_2/Si$ substrate by photo-CVD. In this method, hydrogen-diluted radicals have an important role in forming Si nanocrystals. Under conditions of 5 sccm $SiH_4$ and 20 sccm $H_2$, the maximum density was $1.03 \times 10^{12} cm^{-2}$ and the mean size was 5.64 ± 0.54 nm, which enables this method to facilitate nonvolatile memory application. Even at a low temperature of 150℃, Si nanocrystals have a high crystallinity, which was proven from the TEM image. Furthermore, from the CV characteristics, it was shown that the flat-band voltage shift is about 2.89 V at a ±9 V sweep range. In the photo-CVD, the surface diffusion energy for na...