(A) memory-efficient packet classification engine for high-speed content-based switching

Abstract

To provide various internet services, switching devices are requested to have more intelligence and ability for observing content in application layer. In this dissertation, we discuss a packet classification engine architecture which supports gigabit-rate content-based classification and consumes less memory. First, an area-efficient architecture for concurrent pattern matching and classification is proposed for application to content-based packet switching. The proposed architecture mainly consists of two modules; 1) a finite state machine (FSM) where the cycle-by-cycle state transition occurs and 2) a prefix table for matching the prefix part of the rules to reduce the memory space for storing the information on state transition. Second, a method for content-based classification using results from a string search and a layer 3-4 lookup is proposed. Encoding of the intermediate result value from layer 3-4 lookup enables wire-speed processing while reducing the memory by over 70% co