A 512 × 384 CMOS image sensor in 0.18-μm 1P4M technology with a 5.9-μm pixel pitch has been proposed to compensate for kTC reset noise, image lag and fixed pattern noise. The proposed CMOS image sensor controls the reset voltage using a pixel-level dynamic current source operating in weak inversion and a column-parallel comparator for controlling the current source. The dynamic current source allows realizing a uniform weak current source array even in the case of any significant parameter mismatches. Fixed pattern noise from pixels and column-level readout circuits can be reduced since the reset voltage of each pixel is adjusted to the reference voltage imposed by each column comparator that is also used for single-slope analog-to-digital conversion for pixel readout. A total of $330 μV_{(rms)}$ random readout noise, which is a factor of two improvement over conventional reset operation, has been achieved. We can also suppress fixed pattern noise level to $250 μV_{(rms)}$. The chip operates at 1.8 V and consumes 40 mW excluding I/O and off-chip DAC for a single-slope ADC at 30 fps.
For machine vision applications, image senors with high-spatial resolution are not always required or desirable though the low-resolution image is not sufficient to analyze the details. However, since the amount of data is reduced, the computation can be performed fast which is critical in real-time applications. In addition, the unnecessarily detail information can be filtered out in low-resolution image. In order to utilize all advantages of various resolution images, we have proposed the analog-to-digital conversion structure that is a type of column-parallel multi-bit sigma-delta oversampling ADC using the controlled reset scheme, improving the previous schemes with single-bit sigma-delta converters. We can utilize multi-resolution readout characteristics in digital domain by simple decimation process in the proposed readout scheme. The quantization noise characteristics are a...