SoC design methodology based on c model refinement

Abstract

FPGA-based emulation, which is now widely used in the design and verification of System-on-a-Chip (SoC), is applicable only when the RTL design for the whole system is available thus resulting in a long design turn-around time. In this thesis, we present a new design flow based on a C-to-hardware IMPLEmentation tool (CIMPLE) and a CONfigurable SoC Emulation Platform (CONSCEP) that emulates the on-chip bus system prior to the RTL design of each SoC component. With the emulation environment set up in the early stage of the design process, the design and verification task of each functional block in the SoC can be performed not only faster, but also more complete as a more complete set of test vectors can be applied before the integration. CONSCEP consists of 1) configurable bus components for the given on-chip bus standard, and 2) a set of transactors to link the HDL models of the pre-verified IP blocks with the C models for the behavioral blocks to be designed, or software blocks. CIMPLE translates the C model for a hardware module to a SystemC code, which can be synthesized and directly attached to the CONSCEP as an IP. CIMPLE allows global variables, nested function calls and simple pointer access, which significantly reduces the code migration time. The proposed design flow is demonstrated using a JPEG encoder/decoder system and successfully applied to a commercial MPEG4 video codec chip.