Programmable turbo fecoder for multiple coding standards

Abstract

This paper addresses a small, low-power turbo decoder that is programmable so that it can be easily adapted to multiple standards employing turbo codes. We propose hybrid architecture of hardware and software, which has the small size, low power, and high performance of hard-ware implementation, together with flexibility and programmability of software. It mainly con-sists of a configurable hardware SISO decoder and a 16-bit SIMD processor, which is equipped with five processing elements and special instructions customized for interleaving in order to pro-vide interleaved data at the speed of the hardware SISO. In addition, a fast and flexible incremental block interleaving algorithm running on a parallel processor is proposed. The interleaver generation is split into two parts, preprocessing and on-the-fly generation. The splitting effectively hides timing overhead of interleaver changing. We present detailed descriptions of the interleaving algorithm applied to the W-CDMA and cdma2000 standard turbo codes. The decoder is also capable of Viterbi decoding so as to reduce the cost in applications that use both turbo and convolutional codes. We have implemented the decoder in a 0.25㎛ CMOS technology with five metal layers. It occupies a core area of 8.90㎟ operates at 135MHz, and decodes 5.48Mbit/s bit stream with six feedback iterations. It can decode both of cdma2000 and W-CDMA bit streams.