Techniques for digital frequency synthesis and their applications to communication systems

Abstract

This thesis focuses on techniques of signal processing for designing high-performance digital frequency synthesizers, which are widely used to digital communication transceivers. In this thesis, an implementation technique for the coordinate rotation is proposed to obtain more accurate approximation of sine and cosine functions without large-sized look-up tables. The fine and coarse phase decomposition enables reduction of the size of the look-up tables, and the polynomial interpolation provides accurate sine and cosine evaluations without increasing the size of the tables. Based on the proposed technique, a quadrature-type direct digital synthesizer (DDS) IC was implemented in a 0.35-㎛ CMOS technology, and provides 16-b cosine and sine with a spectral purity greater than 96 dB. It works at 150-MHz sampling rate, consuming about 670 mW. It can be realized using small-sized lookup tables and pipelined arithmetic hardware. The other prototype IC for implementing the quadrature digital synthesizer/mixer function was fabricated in a 0.25-㎛ CMOS technology. It was successfully realized on 0.51-㎟ die area only. It also utilizes the proposed coordinate rotation technique, and allows the digital frequency synthesis with 100-dB spurious-free dynamic range (SFDR) and the digital mixing in the resolution of 14-b input and 15-b output. The prototype IC consumes 460 mW, when working in 330 MHz. In this thesis, a novel spur-reduction technique is also presented. By employing the sigma-delta modulation, a phase accumulator is newly designed, and then the spurs arising from the phase truncation can be reduced. The spectral characteristics of the proposed architecture are mainly determined by the sine-amplitude quantization. A prototype DDS IC based on the proposed spur-reduction architecture was fabricated in a 0.25-㎛ CMOS technology. It uses a 2-b second-order modulator. While the resolution of the phase input of the phase-to-sine converter is 16 b, the SFDR of the prototy...